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Well you don't actually need PLL or 90 degree phase shift but it can help timing failure. Anyway there is no clear picture of your io constraints. You need sdc commands for all adc inputs and based on DDR examples cutting off unrelated edges. I have feeling that your sdc commands for inputs are misleading the reporting, just a guess. I am also not sure why clock pessimism is added to latch clock delay, is clock pessimism removal enabled, though its removal will make slack worse based on your waveforms.
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yes, set_input_delay and set_false_path are used for adc inputs and cutting off edges.
Maybe my sync constraint in the sdc file misleads the Quartus to make a long delay for the DDIO register clock, and this results in the negative setup slack between DDIO register and internal register, i will look into the sdc file carefully.
And you said "is clock pessimism removal enabled", what does this mean? can clock pessimism removal be disabled?from where in Quartus?
Thanks a lot.
ingdxdy
Honored Contributor
