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I need PLL to lock input synchronous clock from ADC, also with 90 degree phase shift to latch input data.
So Removing PLL is unpractical.
path between DDIO and internal fabric is failed in timing analysis.
I used set_input_delay to constrain the sync input, however, it had no influence on my problem.
as i just said, it is the path between DDIO and internal fabric that has negative setup slack, not the path between adc and DDIO.
Best Wishes,
ingdxdy
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Well you don't actually need PLL or 90 degree phase shift but it can help timing failure. Anyway there is no clear picture of your io constraints. You need sdc commands for all adc inputs and based on DDR examples cutting off unrelated edges. I have feeling that your sdc commands for inputs are misleading the reporting, just a guess. I am also not sure why clock pessimism is added to latch clock delay, is clock pessimism removal enabled, though its removal will make slack worse based on your waveforms.
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