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Try remove PLL from design to reduce complexity for now and only use it if then timing fails.
Also you need to identify which path gave above failed waveforms; is it io path between adc and DDIO or internal path after it and have you written sdc with set_input_delay constraints?
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I need PLL to lock input synchronous clock from ADC, also with 90 degree phase shift to latch input data.
So Removing PLL is unpractical.
path between DDIO and internal fabric is failed in timing analysis.
I used set_input_delay to constrain the sync input, however, it had no influence on my problem.
as i just said, it is the path between DDIO and internal fabric that has negative setup slack, not the path between adc and DDIO.
Best Wishes,
ingdxdy
Honored Contributor
