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Yes, clock skew is around 0.86ns, this may be a source of the negative setup slack beside large data IC delay.
I do not know why there is such a large skew between launch and latch clock, because it is out of my control.
Both launch and latch clock come from the same 240MHz clock which is generated by a PLL.
I checked the fitter result, this 240MHz clock is routed through global clock network, so there should not be such a large skew.
The launch clock is fed into IOE to clock the two ddio input registers, while the latch clock is fed into LAB register, does that matter?
does routing to IOE be a difficult task? i have no idea.
Best Wishes,
ingdxdy
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Try remove PLL from design to reduce complexity for now and only use it if then timing fails.
Also you need to identify which path gave above failed waveforms; is it io path between adc and DDIO or internal path after it and have you written sdc with set_input_delay constraints?
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