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After Fittting, TQ reported timing violation.
I checked the data arrival path and found that there was a large IC delay(3.452ns) caused by signal routing from IOE to LAB.
I made serial-to-parralel conversion in LAB unit.
i think 3.4ns is a large delay in nowadays design, especailly in a 28-nm FPGA.
I basically think that Quartus should prevent that large IC delay, even after TQ has reported that violation(i think it is what timing-driven synthesis should do).
Please help, how can i decrease such a large IC delay in CycloneV?
Even put them physically together won't help? I am puzzled, or did i miss something obvious?
Best Wishes,
ingdxdy
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2 or 3 ns is commonly encountered in many devices for clock or data delay (io or internal) so I think you should tackle your timing problem away from this assumption that you must reduce delay. as long as both clock and data are delayed then it doesn't matter what delay is within practical latency range.
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