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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

storing link rates in ATX PLL

Hi I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, In this it uses fpll and stores calibrated link rates for different speeds, can we implem...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Rajesh,


Regarding the ATX PLL storing link rate, Multiple Reconfiguration Profiles is one of the feature supported. Another workaround would be for user to identify the list of registers that need to be changed from a rate to another rate. Then create own controller and perform direct read-modify-write to the target registers. With this method, you can reduce the processing time because you are only changing affected registers. However, the drawback is that you need to code your own controller and need to change the right registers to avoid ATX PLL malfunction.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


  • Rk_Athram's avatar
    Rk_Athram
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi @CheePin_C_Intel

    Thank you for quick response,

    From A10 transceiver user guide,

    For FPLL only having the feature of storing cerebrated results, For ATX PLL calibration is needed to support new VCO frequency.

    so if i change the VCO frequency by changing M,L,N counter values(perform direct read-modify-write to the target registers) for ATX PLL i need to recalibrate after changing from one to other frequency!

    Regards,

    Rajesh