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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

storing link rates in ATX PLL

Hi I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, In this it uses fpll and stores calibrated link rates for different speeds, can we implem...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Rajesh,


Regarding your latest inquiry if you can use the existing logic from display port for ATX PLL, sorry as I do not have visibility into the display port logic and could not really comment. However, based on my understanding, ATX PLL and fPLL should have differences in the internal architecture and registers, I believe you cannot directly use the existing logic.


I would suggest you to open a new thread with request specific to replacing ATX PLL in the DP IP generated design example so that our DP expert could further assist.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi @CheePin_C_Intel

<I believe you cannot directly use the existing logic>

Yes i cannot, i will modify the logic

but Does ATX pll supports storing link rate feature ?

Regards,

Rajesh