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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

storing link rates in ATX PLL

Hi I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, In this it uses fpll and stores calibrated link rates for different speeds, can we implem...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Rajesh,


Thanks for your update. You are right. After performing the dynamic reconfiguration for ATX PLL, you should perform a recalibration to ensure it can function properly. As for the saving of calibration results, sorry as I am not aware of this with the ATX PLL. Probably the example code on Displayport has some customization prepared by Factory.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



  • Rk_Athram's avatar
    Rk_Athram
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi @CheePin_C_Intel

    In display port design for FPLL is used, which having registers to store the frequency band, the similar registers are not available for ATX PLL.

    SNAPSHOT FROM A10 register map excel sheet.

    I need to figure out whether i can use the existing logic from display port for switching speed when i use ATX PLL?

    or i must use only "Multiple Reconfiguration Profiles" for switch between the speed ?

    If possible, please confirm from internal team about my query!

    Regards,

    Rajesh