std_logic_vector(2047 downto 0)

Question

I created a 2048 bit signal and it was originally for combinational logic but I moved it into a clocked process and now my compile time in the fitter takes forever. it used to be fifteen minutes and it just passed an hour and fifteen minutes. and still going. Is this a problem?

altera_forum · Answer

If you move this vector into a clocked process, you are creating a register. A 2048 bit register. It's like creating a RAM bank using the logic elements of the FPGA. The fitter can't route it.

altera_forum · Answer

why do you need such a massive register?

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std_logic_vector(2047 downto 0)

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