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Altera_Forum
Honored Contributor
Honored Contributorstd_logic_vector(2047 downto 0)
I created a 2048 bit signal and it was originally for combinational logic but I moved it into a clocked process and now my compile time in the fitter takes forever. it used to be fifteen minutes and ...
Altera_ForumHonored Contributor
Honored ContributorIf you move this vector into a clocked process, you are creating a register. A 2048 bit register. It's like creating a RAM bank using the logic elements of the FPGA. The fitter can't route it.
