Forum Discussion
Altera_Forum
Honored Contributor
13 years agostd_logic_vector(2047 downto 0)
I created a 2048 bit signal and it was originally for combinational logic but I moved it into a clocked process and now my compile time in the fitter takes forever. it used to be fifteen minutes and ...
Altera_Forum
Honored Contributor
13 years agowhy do you need such a massive register?