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Altera_Forum's avatar
Altera_Forum
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14 years ago

"std_logic_vector" is used but not declared

I worked with the book "Embedded SoPC Design..." from Chu and I have problem with my first (!) VHDL source code I typed from the book. I suppose this is very basic question - sorry about that. ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks, that was it !

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Your code has essentially two components in it. If you have multiple entities in a file, then you need the use statement above every entity declaration.

Cheers,

Dave

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