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Altera_Forum
Honored Contributor
Honored Contributor"std_logic_vector" is used but not declared
I worked with the book "Embedded SoPC Design..." from Chu and I have problem with my first (!) VHDL source code I typed from the book. I suppose this is very basic question - sorry about that. ...
Altera_ForumHonored Contributor
Honored ContributorThanks, that was it !
--- Quote Start --- Your code has essentially two components in it. If you have multiple entities in a file, then you need the use statement above every entity declaration. Cheers, Dave --- Quote End ---
