state machine view problem, need help

s27 bench:

//# 4 inputs

//# 1 outputs

//# 3 D-type flipflops

//# 2 inverters

//# 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs)

module dff (CK,Q,D);

input CK,D;

output Q;

wire NM,NCK;

trireg NQ,M;

nmos N7 (M,D,NCK);

not P3 (NM,M);

nmos N9 (NQ,NM,CK);

not P5 (Q,NQ);

not P1 (NCK,CK);

endmodule

module S27(GND,VDD,clk,G0,G1,G17,G2,G3);

input GND,VDD,clk,G0,G1,G2,G3;

output G17;

wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;

dff DFF_0(clk,G5,G10);

dff DFF_1(clk,G6,G11);

dff DFF_2(clk,G7,G13);

not NOT_0(G14,G0);

not NOT_1(G17,G11);

and AND2_0(G8,G14,G6);

or OR2_0(G15,G12,G8);

or OR2_1(G16,G3,G8);

nand NAND2_0(G9,G16,G15);

nor NOR2_0(G10,G14,G11);

nor NOR2_1(G11,G5,G9);

nor NOR2_2(G12,G1,G7);

nor NOR2_3(G13,G2,G12);

endmodule

Warning: Entity "dff" will be ignored because it conflicts with Quartus II primitive name

Summary Details:

Flow Status Successful - Tue May 13 08:33:06 2008

Quartus II Version 7.2 Build 203 02/05/2008 SP 2 SJ Web Edition

Revision Name s27

Top-level Entity Name s27

Family Stratix II

Met timing requirements Yes

Logic utilization < 1 %

Combinational ALUTs 1 / 12,480 ( < 1 % )

Dedicated logic registers 0 / 12,480 ( 0 % )

Total registers 0

Total pins 8 / 343 ( 2 % )

Total virtual pins 0

Total block memory bits 0 / 419,328 ( 0 % )

DSP block 9-bit elements 0 / 96 ( 0 % )

Total PLLs 0 / 6 ( 0 % )

Total DLLs 0 / 2 ( 0 % )

Device EP2S15F484C3

Timing Models Final

If I change "dff" to "dff1" all places in side the code with a modification in the dff module such as

module dff1(clk,Q,D);

input clk,D;

output Q;

reg Q;

always @(posedge clk)

begin

Q<=D;

end

endmodule

This shows 3 registers but software is not recognizing any state machines