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Altera_Forum
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16 years ago

State Machine- State doesn't set logic as expected

The folowing code is designed to convert a 24 bit value in to 4x 6 bit values to transmit over a 6 conductor cable. At each state I define what my output clock should be by assinging a logic level t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for the tips.

The state machine I had created was designed to latch-out the data on the SendBit(0-3) states and then send a rising edge (DataOutClk) on the LatchBits(0-3) states for the receiver to use to latch the data into the receiver. Unfortunately for some reason the DataOutClk doesn't toggle at every state as I would expect. It seems to skip the middle states. I believe that it enters the states but just doesn't toggle the DataOutClk by setting the GeneratedClk each time.