Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

State A => State B multicycle path?

Is there a way to tell TimeQuest that all signals launched by State A and captured by State B are part of a multi-cycle path? My combinational path delay is too large so i'm adding a timer to delay m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

But if the output of Latch_FF isn't considered to be 'valid' until T2 then

the Downstream_FF won't be 'using' this value until T3 at which point it

will be a solid '1' or '0'.

--- Quote End ---

It is very unsafe design to violate register timing and then wait until it recovers. A register may not end up in the right state if it is violated.

This practice is unavoidable across clk domain transfers (but two synchroniser stages are needed in this case)