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My point is that the statement in bold doesn't apply. The reason is that downstream combinational logic will block the metastable signal from reaching the next register. Only at T2 will the combination logic let the Latch_FF.Q signal through to the next register. At T2 the Latch_FF.Q will not be metastable.
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I think you got confused on something basic.
This may be simpler to understand if, instead we assume Latch_FF will go metastable at T1, we simply assume the delay is so long that it totally overshoots the tSU/tH window at T1 and Latch_FF simply latches the old value.
At the T2 clock edge, two things happen at the same time:
- Latch_FF latches the value at it's input prior to the clock edge
- Downstream_FF latches the value at it's input prior to the clock edge.
So, after T2 clock edge, Latch_FF will (most likely) have a correct value.
But what Downstream_FF will be latching at the T2 clock edge is based on what Latch_FF had prior to the clock edge -- a bad value.
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