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Once again, I agree. The metastability may settle out on the next clock edge, but in the mean time, it may cause other registers down stream to go metastable.
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As explained, this cannot happen in my design since combinational logic will block the metastable signal from reaching the target register at T1.
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In addition to that, it also creates noise in a circuit which can cause crosstalk to other nearby traces.
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Crosstalk inside the FPGA? This is a new concept I have not come across before. If FPGAs were susceptible to crosstalk internally, how can signals belonging to different clock domains be mixed inside the FPGA. This would surely cause internal signal paths belonging to one clock domain to switch randomly with regards to other signals belonging to other clock domains, causing havoc?
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