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Kaz,
multicycle exceptions are not restricted to clock enables.
Consider this example.
Let's say we a have a state machine that in one clock is in stateA, next clock in stateB and next clock in stateC.
always @ (posedge clk) begin
if (state == stateA) regA <= someValueA;
if (state == stateB) regB <= someValueB;
if (state == stateC) regC <= regA - 10 + regB;
end
The synthesis tool may use clock enables to implement this behavior. Or it may simply implement them by feeding back the registers' output via a mux.
But in both cases, we can set a multicycle exception of 2 for the path between regA and regC.
What the multicycle exception tells TQ is that the transitions from regA and regC have 2 clocks to propagate.
The transitions from regB to regC, however, still only have 1 clock to propagate.
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True and I said that multicycle applies in two cases only:
1) latch register is not allowed to clock in (clk enable)
2) launch data is not allowed to change every clock (latch register need not have enable), or both naturally. So yes your register A above is controlled not to change its data onto register C until state goes from A => B => C
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