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If the latch register cares about data every other clock but data may change every clock then you cannot apply multicycle because the register will be affected by violations.
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I see your point, but:
I understand that if Tsu/Th is not met at Latch_FF's D input at T1 (T1 = Tlaunch + 1) then it may go into a meta-stable state at T1. However, since the output of Latch_FF is ignored until T2 and since D is stable well before T2, I would assume that the latch FF would have recovered from a potentially meta-stable condition (at T1) long before T2 (where it needs to clock in the data correctly).
My clock is 125 MHz so there are 8ns from T1 to T2.
Is my reasoning incorrect?
Honored Contributor
