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The key motivator is to mitigate the risk of end of life of off the shelf components
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This would depend on "where" your intellectual property exists, i.e., is your secret sauce in the hardware design or in what the software does.
For example, if your "secret sauce" is in software, and that software is written for an ARM microcontroller, then at a minimum you might need to port your code from ARM7 to Cortex series devices, but there would be no reason to go to an FPGA or SoC FPGA. There are numerous vendors that support the ARM processor architecture, so as long as you are not using exotic interfaces specific to a particular vendor, you have few end-of-life issues.
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We would be looking to mixed signal specifically in the rfid space where there is a need to support legacy and newer technologies with ever increasing security needs between the token and back end.
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I would assume low-power would be a requirement in this situation. FPGAs are not likely to be the best solution.
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I realize the broad question but was throwing out a generality to get a feel . Eg 30.000 gate design 8 months, unit price 25 us.
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The design time depends on the team and the task, its impossible to estimate. The unit cost is the unit cost of the FPGA plus its configuration device. You can find that information now.
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Often we have jumped in and find that 40 % of engineering time is on keeping abreast of the tools and devices as the rate of change results in permanent loss of traction due to new design bedding down and just when stable all the factors of design freeze have moved and we begin again.
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This is highly dependent on the resources you use. If you have to use Altera's IP, and that IP changes for each device, then yes, you have to keep abreast of the tools and devices. However, there are plenty of development kits, so as long as you are prepared to invest in the kits, and provide them to your engineers to "play with", they will be familiar with the different device architectures and IP requirements before you use the devices in a product. There is definitely a non-zero cost associated with changing devices though.
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I get the feeling that the fpga route is for companies that don't have the resources or market volumes for ASIC , so perhaps key decision is if volumes were high enough could we justify an ASIC and if yes the do first iteration on fpga.
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FPGAs are definitely a good vehicle for designing new IP. However, FPGA and ASIC flows are not identical, eg., in an ASIC if you want a particular RAM block, then you can use it, and use it as many times as you want. In an FPGA, you have a fixed set of resources, and so you may have to make some FPGA-specific design decisions. Regardless of this limitation, they reduce the development risk, but they "cost" in that your developer now has to be familiar with an ASIC flow and FPGAs (and FPGA-vendor specific devices and IP).
Cheers,
Dave
Honored Contributor
