Startix V to Arria 10 Poring Resource utilization issues

Hi,

I am currently working on porting the same core logic from Startix V GX to Arria 10 GX. I observe that the ALM utilization in Arria 10 is twice the amount as in the Stratix V device for the same core logic(6000 in arria -10 to 3000 ALM in stratix V). There are also timing closure issues existing in Arria 10 pertaining to the same core logic. These timing errors do not happen in Stratix V for the same clock period.The design that I am porting uses a 256 bit-width memory of height 64. Kindly add some suggestions as to why there is this variation and guidelines for effective porting to Arria 10. While looking at Arria-10 to Stratix-V, the ALM structures look similar, so I am not sure what causes this mismatch.