Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

[STARTIX III][ALTPLL RECONFIG][ALTPLL] Is it possible to change multiplication factor

Hi there, I need to create a clock with a frequency range from 10MHZ to 30MHZ, with a step of 0.25MHZ. I imagine using an alt_pll and a alt_pll_reconfig Ips. pll_clk with an input clock ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It's possible, we always use it. But you may have problem with range: very slow freq from 100 MHz.

Whether or no, you must recompile your design with each step of freq. After each recompile you have to open fitter usages to see PLL options (rewrite it). After that you will have array of PLL parameters for each step. And you may create scan chain for every step from you array. You may use alt_reconfig or write scan chain by you self, never mind...

Good Luck!

Anton