Stabilitiey of macro vs. mega functions in 3000

It depends on what you have learned in the intervening decade :)

Do you know VHDL or Verilog and do you simulate your designs using Modelsim? If you don't, are you interested in learning?

If I was given the task of updating your code, the first thing I would do is to create a testbench that verifies the functionality of the design. I'd use MAX+Plus II to synthesize your design, and then generate a Verilog or VHDL netlist. The testbench would be written in either Verilog or VHDL. That setup would be my 'reference' design.

I'd then either convert the design to Verilog or VHDL, and use Megafunctions where needed. Though in your case, shift-registers, registers, and FSMs could be described directly in the language. The same testbench would be used to test this design, to confirm the functionality of the original design was reproduced.

If you want to take a shot at updating to an HDL, you'll get help on this list.

What function does your design implement?

Cheers,

Dave