STA Timing result much worse with Quartus v20 and later than v17.1

Hello,

Case has been solved through email.

Solution:

I do agree that reusing Synplify netlist in from the v17.1 project could be an issue. Because the .vqm netlist should be optimized for the target Quartus software, ensuring better performance, and the place & route algorithm changes with each Quartus version: https://www.intel.com/content/www/us/en/docs/programmable/683122/18-1/using-synplify-premier-to-optimize-your.html

Plus it is better to provide timing constraints in the Synplify software: https://www.intel.com/content/www/us/en/docs/programmable/683122/18-1/simulation-and-formal-verification.html

Do you plan to continue without Synplify?

I have looked into the timing reports and there are many violations at the RAM area.

I have also checked for Report Unconstrained Paths & Check Timing reports and there are many issues with the SDC constraint. Before you attempt to do any timing optimization you need to fix the Unconstrained Paths reported, or ensure that they can be ignored.

Regards,

Nurina