Forum Discussion
tfan2020
New Contributor
New ContributorSTA Timing result much worse with Quartus v20 and later than v17.1
Hi,
I have a design implemented in Arria10 device, I'm using Synplify_premier v2019 + Quartus v17.1 Standard edition. Now I want to upgrade the Quartus version to v20 later, e.g. v22.1.
The iss...
Nurina
Regular Contributor
Regular ContributorHello,
Are you using Quartus Pro or Standard? These documents tells you how you can perform Automatic Gated Clock Conversion on Quartus Pro and Standard:
- https://www.intel.com/content/www/us/en/docs/programmable/683236/22-1/automatic-gated-clock-conversion.html
- https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/auto-gated-clock-conversion.html
This should be sufficient to convert gated clocks. However from a timing perspective, I cannot confirm if this would improve the slack because I do not know the root cause of the timing violation in your design.
You can share your design through e-mail for privacy purposes. I'll drop an e-mail to you.
Regards,
Nurina
