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Mark13's avatar
Mark13
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5 years ago

SSTL-2 Class I outputs with 8mA drive strength?

Ì am using a NIOS-processor in a Cyclone IV EP4CE55F23I7N. Connected to the FPGA is a DDR-SDRAM with differential clock input. The clock is outputted from FPGA via SSTL-2 Class I outputs. If no exter...
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi there

Table 6–2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pdf shows the available current strength setting for different IO standard. It also stated that when you use programmable current strength, on-chip series termination (RS OCT) is not available. Those are the optimum setting done by the characteristic team.

We can refer to below link for more information:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd08292012_329.html

Thanks.

Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    4 years ago

    Hi there

    We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Eng Wei