SRAM view content

Are really simulating as you've indicated or are you debugging?

Jake

Thanks Jake for question, here are more details :

I've implemented a single port SRAM 8 x 4096 bytes which is written / read by my FPGA application. During vector wave simulation, I'd like to view at some point (on timescale) memory contents (to test if my process really updates that particularly cell).

If I was in C, I'd setup some breakpoint in code and simple watch memory at desired address from IDE (step by step). For the moment I haven't Cyclone board physically, so I must limit to simulation.

Btw, excuse me for this newbie question: on FPGA exists this IDE concept of running step by step just written code?

And one more big misunderstanding, if we already are at SRAM thread: speaking about Cyclone III - from its datasheet I read memory blocks are running at 315MHz. How is this possible since in Quartus simulation (classic) I noticed data is available for read no quicker than 10nS after addresses stabilize (as a good old fashion SRAM I saw) which means at most 100MHz.

Thanks,

I use standard simulation offered in Quartus. I generated a vector waveform, I added all in/out signals I need and I initialized over time "in" signals with whatever desired.

The I run simulation and watch "out" signals.