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Honored Contributor
Honored ContributorSRAM interface timing discrepancy from Quartus-II 7.0 and 9.0
I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
Altera_ForumHonored Contributor
Honored ContributorHi,
Tsu and Th plus fast input registers are meant for your inputs from sram. Tco and fast output registers are for outputs to sram. If the tool rejects these constraints on grounds of no path available then this indicates that there is no register on those paths at one end and this is a good indication that some of your inputs or outputs are not registered. You better register every input and every output in order for the constraints to be applicable and for timing to be consistent.
