SRAM interface timing discrepancy from Quartus-II 7.0 and 9.0

well, i had recalculated _ALL_ timings and also verified them with a LeCroy Scope in real life target. as nearly all fpga's here rely on the same sources and use the same software binary, i had to do this a dozend times.

also check your quartus settings. for the sdram if here, i rechecked that fast input outregisters and other settings are as needed. and i guess you have checked the pin output current settings to prevent over and undershots. thats why i checked it with a very fast scope