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Altera_Forum
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16 years ago

SRAM interface timing discrepancy from Quartus-II 7.0 and 9.0

I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
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Altera_Forum
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16 years ago

Hi Michael,

Thank you so much for you sharing your experience with me. Really appreciated.

I started from Quartus-II 5.0 more than 4 years ago. Every time when I upgraded Altera design software, I always had different issues. Up to Quartus-II 7.0, I did not want to take risk to upgrade it 7.2 becuase it is not backwards compatible. Now, I am going to start a new design and ideally I can use the latest design software. I upgraded it to 9.0 SP1 and tried to the existing design. Then I found the problem.

I agree with your "from quartus 8 and never the new calculated values must be used." Beyond this, I have lots of other timings as well in my design. Should I re-calculate all the timings, verify and validate all of them?

Best regards,

BC