Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSRAM interface timing discrepancy from Quartus-II 7.0 and 9.0
I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
Altera_ForumHonored Contributor
Honored Contributorhmmm i had different experiences.
startung with quartus 4.2 the product family design was finished in quartus 7.2 with quartus 8 some of these targets were not working properly and the more the enviromental temperature differs from 25 degree celcius the more worse these targets were and some others started to fail too. at the end, i had to recalculate the pll phase again with newer reported values and all targets were working again as expected. up to quartus 7.2 no change needed in phase shift, from quartus 8 and never the new calculated values must be used.
