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Altera_Forum
Honored Contributor
Honored ContributorSRAM interface timing discrepancy from Quartus-II 7.0 and 9.0
I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
Altera_ForumHonored Contributor
Honored ContributorIt might affect timing a little bit by heating up and then cooling down the board. I don't think that it can cause as much difference as 2ns. My target boards are in production and don't have temperature problem.
