sram and vga problem ?

regarding my prev post...............

i thought i'd start reading a .bin file into the BRAM first before trying for the bmp file

unfortunately the code is not responding:

entity files is

PORT(

clk_in :in std_logic;

output : out bit_vector(2 DOWNTO 0);

out1 : out std_logic_vector(6 DOWNTO 0);

we : in std_logic;

input : in std_logic_vector(3 DOWNTO 0);

rst: in std_logic);

end files;

architecture Behavioral of files is

type ramtype is array(0 to 7) of bit_vector(2 downto 0);

impure function file_io (inFile : in string) return ramtype is

file Prog: text is in inFile;

variable L: line;

variable VALUE : bit_vector(2 DOWNTO 0);

variable RAM1 :ramtype;

begin

for I in ramtype'range loop

if NOT endfile(Prog) then

readline (Prog, L);

read (L, RAM1(I));

end if;

end loop;

return RAM1;

end function;

signal in_data : bit_vector(2 DOWNTO 0);

signal RAM : ramtype := file_io("demo.bin");

signal address : std_logic_vector(3 DOWNTO 0);

begin

process (clk_in) IS

begin

if clk_in'EVENT and clk_in ='1' then

if (we = '0') then

RAM(conv_integer(input)) <= in_data;

output <= in_data;

else

output<=RAM(conv_integer(input));

end if;

end if;

CASE input IS

WHEN "0000"=>out1<="1000000";

WHEN "0001"=>out1<="1111001";

WHEN "0010"=>out1<="0100100";

WHEN "0011"=>out1<="0110000";

WHEN "0100"=>out1<="0011001";

WHEN "0101"=>out1<="0010010";

WHEN "0110"=>out1<="0000010";

WHEN "0111"=>out1<="1111000";

WHEN "1000"=>out1<="0000000";

WHEN "1001"=>out1<="0010000";

WHEN OTHERS=>NULL;

END CASE;

end process;

end Behavioral;

The in_data seems to be redundant and confusing , but if i dont assign the ram to an unassigned signal ie when we ='0' then the RAM is instantiated as distributed instead of BLOCK

The bin file is just :

demo.bin

000001010011100101110111

( 0 to 7 in 3 bit)

can anyone help me with this file_io problem...

?

or is ther something fundamentally wrong with this approach