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Actually an SPI slave where all the inputs are synchronised with a double register-chain doesn't need to be constrained.
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My concern is that be cutting all the spi paths you cant guarantee the fitter is going to place the registers in a repeatable way. I believe as long as the internal clk is a lot faster than the spi clock like 10x, its not going to be a problem but as the freq increases you might get one fit work and one fit not work.
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IMO the so-called SPI clock isn't a real clock as it isn't continuous. The original author should have called it Strobe.
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Yes from the FPGAs internal point of view its not a true clock but from the spi data point of view it is a clock. IMO I would prefer the hdl signals to match the standard interface signal names but in the end the naming is negligible.
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