SPI Slave Timing Constraint Question

Hmm thats a good question. When starting out I thought this method seemed to better fit with the data flow control I have surrounding the slave component. It also required less asynchronous design and less handshaking with the internal clock domain. When nss and sclk are idle I would be using control signals to update buffers etc. rather than clocking them per normal synchronous design. On the upside it would increase the max spi freq the component could support.

I am putting together another slave component with the spi sclk directly controlling the shifting as per your suggestion. But for the sake of argument would the timing constraints I have suggested constrain the original design?

James