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Honored Contributor
Honored ContributorSPI Master Timing Constraints
I know there is a lot of discussion on this board regarding timing constraints, but I couldn't find this topic well addressed. I have a system where my FPGA interfaces to an ADC using a SPI lik...
Altera_ForumHonored Contributor
Honored ContributorI don't see anything wrong with nor do I have a better idea now. :)
You might not need a PLL though, just using the falling edge of the received SCLK might work. Note that you'll have to treat the incoming SCLK as an asynchronous clock, in regard to SCLK and others. What are the values you got for min and max input delay?
