SPI Master Timing Constraints

Thank you very much, this was very helpful. I too am very concerned about closing timing.

After going through the exercise I think I have found that while I can close timing on the output signals interface, it will not be possible to close timing on the MISO using the current hardware approach. However, I do need to run at these speeds. I think I have come up with a method to allow this. If I loop back the SCLK and the CSn, that should set up a source synchronous interface for the MISO. If I then feed that SCLK into a PLL and phase shift as needed to center in the valid data window I should be able to both run at my desired speed and meet timing. Then for timing purposes, I only need to be concerned with the possible skew between signals similar to the what I was able to do for the output signals.

Any thoughts on this approach?