SPI Master Timing Constraints

Your clock constraints look incorrect; you're just creating 3 identical virtual clocks.

Instead, you should do it like this:

create_clock -name clk -period $mainClockPeriod [get_ports clk# Constrain the clock that actually goes into the FPGA

derive_pll_clocks# Constrain PLL generated clocks

create_generated_clock -name data_io_clk -source $pllOutput [get_ports $sclkOutputPortName]# Create a derived clock on the SCLK output pin

You don't need a virtual clock for this case, because the clock is provided by the FPGA. So the CS, MOSI and MISO signals should all be constrained in relation to data_io_clk.

What you need to do for MISO is the same thing you did CS/MOSI: take into account all your clock/signal buffers and the ADC's MISO tCO and figure out what's the minimum and maximum delay between a SCLK rising edge and a MISO transition, seen at the FPGA pins.

In case of doubt, drawing the timing diagram always helps.

Your output delay calculations look a bit more complicated than they should, but I didn't examine it carefully so they may be all right.

It should be something like

max output delay = adc tSU + sum of all max buffer delays on data path - sum of all min buffer delays on clock path

min output delay = -adc tH + sum of all min buffer delays on data path - sum of all max buffer delays on clock path

For the input delay, it should be

max input delay = max adc tCO + sum of all max buffer delays on data path + sum of all max buffer delays on clock path

min input delay = min adc tCO + sum of all min buffer delays on data path + sum of all min buffer delays on clock path

You mention that your delays are > 1 clock and you'll use delay states to handle this. This is OK, but you may need to add multi-cycle exceptions to adjust the constrains, or TimeQuest may never give you a "pass" (even if your design might actually work).

That said, I'm not sure you'll be able to achieve timing closure for 32 MHz operation, given all those delays.. you may have to run with a slower SCLK.

I'll leave your last question to when you've fixed these issues. :)