Honored ContributorI wanna implement spi communication between cyclone ep1c240qc8 and freescale dz60,but some problems comes out.freescale dz60 was configured as the master,while ep1c240qc8 as the slaver.when dz60send data, the data ep1c240qc8 received are all zero, I don't know what the matter is. of course, some guys told me to add a fifo, but I don't know why. so i came here to ask for help...
Honored ContributorUse a Signaltap probe on your SPI signals inside the FPGA, it will let you trace the problem. The first thing you need to find out is whether the problem comes from inside the FPGA or outside.
Honored ContributorObviously, it's impossible to give a detailed answer without knowing the design details.
Honored Contributor9/10 times you can spot the problem by just hooking up a logic analyzer and seeing if your master is doing what you think it's doing. Probe all your lines MOSI, MISO, CLK, CS and see what is going on with your master. Also, it's always good to hook up an oscilloscope and look at signal quality. Are there lots of ringing? Overshoot and undershoot causing false logic transitions? Your question is far too generic to suggest anything other than to suggest generic solutions.
