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Altera_Forum's avatar
Altera_Forum
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12 years ago

speed up read of embedded RAM from external bus interface

Hi all! My FPGA (CycloneII) is a slave on an MCUs external bus interfaces (EBI). The MCU shall read the content of FPGAs embedded RAM preferably without wait state. Unfortunately I don't know ye...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You mention the MCU requiring the data to be presented for another clock cycle - is that right? If so, it's not timing constraints that's the problem - it'll be the logic.

You will need to configure your MCU in a way as to postponing changing the RAM address and read selects for an additional clock cycle. If it was a Nios processor, external peripherals can be configured to add 'wait states' while the peripheral gets the data ready. Is that not what you need?