Altera_Forum
Honored Contributor
Honored Contributorspeed of fpga
what is the appropriate clock frequency which i can select for a cyclone III fpga(ep3c25144i7)and is there any relatin between the speed of fpga and clock frequency???
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Altera_ForumIt depends entirely on your design. When you compile something in Quartus it will give you the maximum frequency a given compiled design can run at. Adding pipeline stages to an existing design can help increase its maximum frequency, at the cost of a higher latency. Speed is highly correlated to clock frequency, but it also depends on what you call speed. Optimising the design can be more important for speed than the actual clock frequency.
- Altera_Forum
I am using 50MHZ frequency and while transmiiting the data it takes so much of delay at the receiver end I apologise for the silly questions as i am new to the fpga design
- Altera_Forum
What kind of data, what kind of interface? What delay do you get and what would you like to have instead?
