Specifying LUT's

Hi,

I'm currently trying to port the CERN WhiteRabbit TDC, which was originally written for Spartan FPGAs, to Cyclone4.

The code contains a ring oscillator build out of hand specified LUTs:

architecture rtl of tdc_ringosc is
signal s: std_logic_vector(g_LENGTH downto 0);
attribute keep: string;
attribute keep of s: signal is "true";
begin
    g_luts: for i in 0 to g_LENGTH-1 generate
        g_firstlut: if i = 0 generate
            cmp_LUT: LUT2
                generic map(
                    INIT => "0100"
                )
                port map(
                    I0 => s(i),
                    I1 => en_i,
                    O => s(i+1)
                );
         end generate;
         g_nextlut: if i > 0 generate
            cmp_LUT: LUT1
                generic map(
                    INIT => "01"
                )
                port map(
                    I0 => s(i),
                    O => s(i+1)
                );
         end generate;
    end generate;
    s(0) <= s(g_LENGTH);
    clk_o <= s(g_LENGTH);
end architecture;

There does not seem to be an equivalent primitive for Cyclone/quartus that supports the same functionality. It seems that either LUT_INPUT/LUT_OUTPUT or LCELL should be used instead, but I cannot figure out how to use them. The documentation of the primitives is short, at best, the "Designing with Low-Level Primitives" user guide does not contain more info and the Stratix Advanced Synthesis Cookbook does not mention them at all.

Could you point me to a description of how to use these primitives or something else I could use instead to solve this problem?

Thanks in advance