Source Synchronous interface with Cyclone 10 GX Transceivers

Background and Questions:

1- Background:

For the source synchronous interface with Cyclone 10 GX transceiver, I am planning to use the following clock arrangement (Please see the attachment file): You can also find the same figure at page 70 Figure 16 in the following document:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf

https://alteraforum.com/forum/attachment.php?attachmentid=15624&stc=1

There are 3 locations in the figure shown below:

1- Input Ref Clock Pin

2- PLL Clocks Driving Transceiver Serializer

3- Transceiver Output Pins

question:

I want to adjust the clock phases of PLL clocks which are driving serializer based on the rising edge of input ref clock pin(Please note that there will be only one ref input clock pin for all 5 transceivers ) for all 5 transceiver which are going to be used in source synchronous interface ( 4 data and 1 clock ).

is there any limitation or restrictions for implementing this configuration?

please note that the transceiver clock (1.25 ghz which gives 2.5 gbps ) will be integer multiple of input clock frequency for the alignment purposes.