Source Synchronous interface with Cyclone 10 GX Transceivers

Please see the document at the following link: page 70 figure 16 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf in Which input reference clock which drives ATX PLL, FPLL, CMUPLL, then the output of PLLs drives Clock Generation Block (CGB) , after that the output of Clock Generation Block (CGB) drives the registers at the PMA section of transceivers.

My question is : Is there any limitation by using the same reference clock to drive 5 transceiver then to use one of them as clock and 4 of them as data to implement source synchronous interface at 2.5 Gbps ( Clock will be 1.25 Ghz ) ?