Forum Discussion
Altera_Forum
Honored Contributor
14 years agoSorry, you can create a virtual generated clock, but I believe you get a warning that it couldn't find a connection between the generated clock and this clock and latency was not included. So if you report_timing -detail full_path, you'll see that the delays to SCLK_ADC1 are not included, so it's not really doing what you want. At this point it's the same thing as a regular virtual clock. (It gets the waveform from the generated clock, but not the delays, which is the important part for source-synchronous interfaces.)