source synchronous interface or virtual clock?

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(3) You can't do a virtual clock based on a generated clock. I tried the same thing and .sdc syntax doesn't allow it. So you just use the generated clcok on sclk for your input.

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Really? I use the following constraints and it is accepted:

create_generated_clock -name SCLK_ADC1 -source [get_pins {inst15|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 4 [get_ports {SCLK_ADC1}]

create_generated_clock -name SCLK_ADC1_virt_in -source [get_ports {SCLK_ADC1}]

Here is the Clocks Summary in TimeQuest:

http://www.alteraforum.com/forum/attachment.php?attachmentid=5011&stc=1&d=1320735423