source synchronous interface or virtual clock?

Close, but:

(3) You can't do a virtual clock based on a generated clock. I tried the same thing and .sdc syntax doesn't allow it. So you just use the generated clcok on sclk for your input.

(4) Since you can't do (3), you can't do this one either.

(5) Your set_input_delay will have its -clock option based on SCLK. The -max value is the max roundtrip delay external, i.e. the board delay from FPGA's SCLK to ADC, the max Tco of ADC and board delay back to FPGA. The -min value it the min of all those values.

Though your interface is really slow, are you doing anything on the output side to center align the clock and data, i.e. are you inverting the clock going out or something? (I'm assuming this is single-data rate). Take a look at my source-synchronous document on the alterawiki site, as it talks about different approaches for this.