source synchronous interface or virtual clock?

Josyb, you are right about the definition of "source synchronous", but here Rysc is just mentioning about my application, where FPGA sends out SCLK and DOUT to an ADC, and ADC uses SCLK as its clock to send its data DIN to FPGA. SCLK and DOUT form the "source synchronous" interface.

Rysc, thank you for clarifying the concept for me.

So I think in my application, I need to constrain the ADC interface with the following:

(1) use create_generated_clock to constrain SCLK

(2) set_output_delay to DOUT with respect to SCLK

(3) use create_generated_clock to create a virtual clock which is generated from SCLK

(4) use set_clock_latency on this virtual clock to estimate board delay/skew of SCLK as it reaches ADC

(5) set_input_delay to DIN with respect to this vitual clock

Is that right? Sorry for asking such detailed things.

Thank you all!