source synchronous interface or virtual clock?

At 20MHz, you can do it either way and close timing. That being said, one is correct and one isn't, depending on how your design is laid out. Since you're sending a clock to the ADC and getting back data, it is source-synchronous, and the delay for the internal clock to get out of the FPGA will be used in all calculations. If the ADC were being clocked by an external clock, then a virtual clock would be the correct method, since the delay for you to get the clock off chip has no bearing on timing analysis. You basically want the constraint to represent what's occuring in hardware as best you can.