source synchronous interface or virtual clock?

Thank you for the reply, Rysc.

Yes, the max clock rate of ADC is only 20MHz (it is AD7928 of Analog Devices). I assume in this case, using source synchronous style or virtual clock will not make a big difference in the result of timing analysis, but source synchronous style is more correct in concept. Am I right in saying so?

I compare the results of timing analysis with these two methods. Under the same contraint, it seems TQ estimates a smaller clock uncertainty of SCLK in source synchronous style than it does in virtual clock.